Tutorials

Tutorial I – Unlocking Material-to-System Innovation with AI

Hussam Amrouch – Technical University of Munich, Germany

We are entering a transformative era where AI is not only advancing our understanding of the world but also might revolutionize the design and development of semiconductor technologies and chip design. As technology scaling faces fundamental physical and reliability challenges, a holistic, material-to-system co-optimization approach is becoming essential. In this keynote, we explore how AI can serve as a unifying force across the semiconductor design stack—from material and device optimization to system-level implementation. We demonstrate how AI algorithms can accelerate device physics simulations, enable faster development of transistor compact modeling, and offer unprecedented speed in standard cell library characterization. We highlight how AI empowers designers, for the first time, to capture and propagate awareness of aging- and defect-related phenomena—originating at the material and device level—all the way to GDSII and final sign-offs. We further discuss the critical importance of AI-driven methodologies in emerging domains such as emerging non-volatile memories and cryogenic CMOS, where the assumptions of classical semiconductor modeling break down. Finally, we demonstrate how neural networks can be effectively employed in transistor compact model offering unprecedented speedup in SPICE simulations with an accuracy error of below 0.1%.

Tutorial II – Reliability of Silicon-based Transistors processed at low temperatures

Xavier Garros – CEA-Leti, France

3D Sequential Integration (3DSI) is a promising alternative to continued technology scaling, enabling energy-efficient and cost-effective circuit design through the sequential stacking of active device layers. A key challenge, however, is the requirement for low-thermal-budget processing to preserve the integrity of underlying layers. This constraint raises concerns regarding the reliability of low-temperature transistors and remains a major barrier to large-scale adoption. This tutorial revisits the critical challenges associated with meeting reliability requirements for low-temperature silicon-based CMOS transistors, with a primary focus on bias temperature instability (BTI) in both n- and p-MOSFETs for digital and analog applications. A systematic investigation of the impact of thermal budget on BTI will be presented, highlighting a distinct transition in BTI behavior for processing temperatures below 600 °C. Advanced characterization and modeling techniques, including the CET map approach, will be employed to identify the oxide traps responsible for BTI in both device types. We will benchmark several process optimization strategies aimed at improving low-temperature oxide quality, including oxide growth methods, gate-stack engineering (TiN versus polysilicon), and post-deposition curing treatments such as hydrogen annealing and nanosecond laser annealing (NLA). Finally, hot-carrier reliability will be examined, with particular emphasis on the role of oxide traps in low-k spacers.

Tutorial III – CMOS product yield and reliability risk: Plasma Induced Damage (PID) past, present and future nodes

Andreas Martin – Corporate reliability department, Infineon Technologies AG, Germany

Plasma processing-induced charging damage (PID) is a significant yield and reliability risk for integrated circuits. A vast number of investigations have been published since the early 1990s. Prevention of PID is typically achieved through thorough process qualification and comprehensive design-rule definitions. However, in recent years, product failures related to PID have been reported in the literature for state-of-the-art technologies featuring highly isolated well configurations and complex, large-area circuits. This indicates an urgent need for refined PID design rules, which have not yet been fully adopted across the semiconductor industry.

This tutorial will present the background of PID and highlight the various failure modes associated with specific process options and circuit configurations. Examples supported by experimental data will be provided, and safe design areas for circuit designers will be defined. All topics will be discussed with reference to key publications from major international journals and conferences.

Content:

• Introduction: basic degradation mechanisms
  • Degradation and charge trapping in dielectric layers
• Failure modes
  • Metal interconnects at the gate electrode
  • Metals at source, drain, and well regions in SOI technologies
  • Well charging in isolated wells
  • MIM capacitor degradation
  • Impact of PID on metallization processes
• Detection and characterization of PID
• Circuit-level protection against PID
• Design-rule checks for products
• Standardization efforts
• Outlook: PID in advanced technology nodes

Tutorial IIII – Introduction to SiC power MOSFET technology and reliability

Peter Moens – onsemi Power Solutions Group, Belgium

In this tutorial we will cover the basic aspects of both planar and trench gate SiC power MOSFET device technology and their reliability. The aim is to provide the audience with insight into the status of the reliability of SiC power devices. The following topics will be addressed:

• Characterization of the SiC/SiO₂ interface by charge pumping and ultra-fast BTI measurements. From the latter the capture and emission time constant maps are derived.
• Identification of the physical nature of the interface point defects through electrically detected magnetic resonance (EDMR)
• Gate Switching instability
• Gate oxide reliability (TDDB) and lifetime. Comparison of SiC/SiO₂ to Si/SiO₂
• Reverse bias reliability
• Cosmic ray susceptibility
• Short circuit withstanding time
• Bipolar degradation

Finally, we will provide an outlook to “Moore’s law for power devices” and where we believe SiC will be heading into the future.