Keynotes
Keynote II – Technology Strategies for Evolving Compute Challenges
Ben Kaczer – imec, Belgium
The rapid proliferation of large language models and agentic AI-driven applications continue to fuel an unprecedented demand for compute across datacenters and edge systems alike. The deceleration of CMOS scaling—yielding diminishing improvements in power, performance, area, and cost (PPAC) from node to node—and the escalating costs of new designs and wafer manufacturing, present a dual challenge for compute ecosystem. Addressing these constraints requires rethinking the problem from a tops-down, system-level perspective, where new approaches beyond traditional scaling may be required. This talk will explore key bottlenecks limiting compute system performance: compute density, power delivery and efficiency, thermal management, and memory capacity and bandwidth. It will highlight emerging technology strategies to overcome these barriers – continued dimensional scaling, novel device architectures, new materials and innovative integration schemes using advanced interconnect technologies. Introduction of these options will need deeper understanding of failure modes with new reliability considerations. This will also require fresh approaches to failure modelling and system robustness to ensure sustained performance throughout the operational lifetime.
Dr. Ben Kaczer is a Scientific Director in the Advanced Reliability Robustness and Test (AR2T) department at imec. Dr. Kaczer received M.S. degree in Physical Electronics from Charles University, Prague, in 1992 and M.S. and Ph.D. degrees in Physics from The Ohio State University, in 1996 and 1998, respectively. In 1998 he joined the reliability group of imec, Leuven, Belgium, where his activities have included the research of the degradation phenomena and reliability assessment of SiO2, SiON, high-k, and ferroelectric films, planar and multiple-gate FETs, circuits, and characterization of Ge, SiGe, III-V, MIM, and TMD devices. He has co-authored more than 600 journal and conference papers with 20,000 citations (Google Scholar) and 5 patent groups related to device and circuit reliability, presented a number of invited papers and tutorials, and co-received 6 IEEE International Reliability Physics Symposium (IRPS) Best and Outstanding Paper Awards, 2 IEEE IPFA Best Paper Awards, and the 2011 IEEE EDS Paul Rappaport Award. Dr. Kaczer has served twice as the chair of the Characterization, Reliability and Yield subcommittee of the International Electron Device Meeting (IEDM; 2007 and 2015) and as a member of various subcommittees of the IRPS (2002—2016) IRPS management committee (2017—2026) and is currently serving as the General Chair of upcoming IRPS 2027. He was the General Chair of the Semiconductor Interfaces Specialists Conference (SISC; 2006) and continues to act as the conference secretary (2007—). He co-organized the INFOS conference (2005), and served on the INFOS, WoDiM, IPFA, and ICICDT conference committees. He has served on the Editorial Board of IEEE Journal of Transaction of Electron Devices for three terms (2011—2019).
Keynote III – Integrated Workflows for Physical Failure Analysis
Tomáš Vystavěl – Thermo Fisher Scientific
As semiconductor devices become more structurally complex, physical failure analysis increasingly depends on how effectively localization, site-specific preparation, and final analytical confirmation are combined into a coherent workflow. The key challenge is not only to identify the failure site, but to move efficiently from that location to reliable root-cause determination. This contribution outlines an integrated workflow for physical failure analysis, spanning localization, precision sample preparation, and high-resolution physical analysis. The focus is on how these steps work together to improve the success rate, reduce the time to answer, and increase confidence in the final diagnosis. Rather than concentrating on a particular device architecture, the contribution highlights a workflow-oriented approach that supports advanced semiconductor development and manufacturing.
Tomáš Vystavěl, is R&D Director at Thermo Fisher Scientific, where he leads architect teams developing platforms for advanced microscopy and semiconductor workflows. His background is rooted in electron microscopy and materials characterization, with extensive experience across SEM, TEM, and FIB technologies in both research and product development. He has contributed to the development of new microscopy methods and workflow solutions across multiple application areas. He currently focuses on platform and workflow development, bringing together instrumentation, software, and application expertise to support more integrated and effective solutions.
