Invited Talks

Wide bandgap (WBG) power semiconductors give significant advantages, but they also introduce new reliability risks and qualification demands. This talk highlights the challenges specifically shared by SiC Vertical MOSFETs and GaN Lateral HEMTs. Understanding the reliability limits of both technologies is important to meet the low-DPPM levels expected by customers and already achieved by mature Silicon MOSFETs. Dedicated dynamic measurements are needed to reveal new degradation mechanisms and develop related failure models. In addition, there is the desire to provide universal degradation models for each technology to be applied to a large portfolio of products with a variety of designs and application relevant needs. These insights shape our qualification strategy as a company and the demand for tailored industry-wide WBG standards. Managing extreme thermal and electrical stress during dynamic testing is particularly challenging, but it is important to balance manufacturing constraints with strict reliability targets. The SiC Vertical MOSFET shows its advantages in high-voltage and high-power applications, leveraging high thermal conductivity and moderate-to-high switching frequencies. We review its primary degradation mechanisms and discuss reliability tests used to evaluate its robustness under realistic operating conditions. Particular attention is given to gate oxide degradation, interface state generation, threshold voltage instability, and degradation induced by repetitive switching stress. While high temperature blocking condition and gate stress are primarily used to assess static reliability and gate oxide robustness, gate switching stress and other dynamic tests are essential for investigating mechanisms that arise under application-relevant switching conditions, as well as for defining production screening limits and guard bands to ensure the highest quality. Similar to the SiC MOSFET, the GaN Lateral HEMT requires also dynamic testing to capture degradation occurring only under switching stress. GaN devices show their advantages for medium-voltage and medium-power applications with their ultra-low specific on-resistance and ultra-high switching frequencies. Operating under extreme conditions introduces degradation mechanisms that a traditional qualification strategy may not reveal. Characterizing these mechanisms can ensure high reliability for large-scale deployment.

Cryogenic low-noise amplifiers are essential parts of today’s quantum computers and are primarily employed in the readout path at the 4 K stage to read the qubit states. Their performance and reliability directly impact the quantum computations, e.g. through the readout fidelity. As one of the few active, i.e. power-dissipating, cryogenic devices used already today, there are strict requirements placed in terms of noise-levels, power, stability and robustness. To support ever increasing qubit numbers, improved amplifiers will be desirable in the future. In this presentation, we demonstrate our cryogenic III-V high-electron mobility transistor technology based on the InGaAs/InP system. We show how noise properties depend on temperature, and how this dependence arises from various traps and defects across the heterostructure that can be effectively suppressed with quantum well engineering. We also describe thermal effects, in particular self-heating, which is one of the primary limits of noise and reliability in these devices. Several self-heating measurement methodologies are examined, such as quantum thermometry, which is able to determine both the intrinsic electron temperature as well as associated scattering mechanisms throughout the device self-heating process. Power semiconductors are vulnerable to thermo-mechanical stress due to the use of solid-metal interconnect technologies such as wire bonding, soldering, and sintering. This presentation showcases a successful usage of room-temperature Gallium-based liquid-metal pastes for chip-level packaging of SiC MOSFETs. All chip-critical interconnects (die-attach, topside, and gate connections) are implemented using liquid-metal, which remains liquid during operation. We tested the SiC MOSFETs for thermal and reliability performance. Liquid-metal packaged SiC MOSFETs showed improved thermal performance and an order of magnitude increase in power cycling lifetime. Notably, the liquid-metal pastes are contained without the use of any encapsulation.

Due to miniaturization and heterogeneous integration of chiplets in the semiconductor industry, a need for electrostatic discharge (ESD) testing of die-to-die (D2D) interfaces has emerged. Current ESD testing methods, such as transmission line pulsing with switching relays, cannot reliably replicate fast D2D ESD events. Hence, novel pulse generation schemes reducing the transition time to below 50 ps are required. This work presents two methods of picosecond pulse generation with broadband radio-frequency amplification for D2D ESD testing. A high-speed arbitrary waveform generator is leveraged to generate short pulses achieving transition times down to 6.4 ps and amplitudes up to 28 V after amplification. Pulse generation with step recovery diodes yields transition times below 30 ps and amplitudes up to 19 V after amplification. While pulse generation with step recovery diodes is simple, less costly, and yet effective, the approach using high-speed arbitrary waveform generation shows overall better results. The presented pulse generation methods can be applied to future ESD testing of D2D interfaces in heterogeneously integrated devices.

As semiconductor memory technologies continue to scale into the sub-10 nm regime, accurate endpoint determination during focused ion beam (FIB) thinning has become a critical challenge for transmission electron microscopy (TEM) sample preparation and failure analysis. Conventional passive auto thinning (PAT) workflows rely on predefined fiducials and operator interpretation of processed scanning electron microscopy (SEM) images, limiting endpoint precision and increasing susceptibility to process variability, beam instability, and human error. This study presents an autonomous FIB thinning methodology, termed Active Auto Thinning (AAT), that integrates machine vision, artificial intelligence (AI), probability-based endpoint prediction, and image interpolation algorithms for real-time control of FIB milling in advanced DRAM and NAND devices. The proposed framework utilizes sequential Slice-and-View SEM datasets to reconstruct three-dimensional device geometry and train AI models capable of recognizing evolving cross-sectional features as milling progresses. Rather than relying on image data optimized for human visualization, the system analyzes detector-derived information directly, preserving high-frequency structural information and enabling enhanced endpoint sensitivity. During operation, probability maps generated from real-time SEM images are combined with interpolation-based distance estimation to predict the remaining distance between the current cut face and the target region of interest. A closed-loop control architecture continuously updates process parameters and autonomously determines milling termination conditions. Experimental validation was performed using advanced FIB-SEM platforms and applied to leading-edge memory devices. The AAT workflow demonstrated reliable identification of target cut faces, robust compensation for beam and process variations, and autonomous operation without operator intervention. Compared with conventional PAT methods, AAT produced thinner and more uniform TEM lamellae, achieving specimen thicknesses near 10–20 nm while maintaining nanometer-scale endpoint accuracy. Statistical evaluation across multiple DRAM samples yielded an average lamella thickness of 15.3 nm with a 2σ variation of 1.26 nm and target-centering accuracy within 0.72 nm (2σ). The resulting TEM specimens exhibited reduced three-dimensional projection effects, improved critical-dimension metrology capability, and enhanced structural fidelity. The implementation of AAT represents a transition from automated to truly autonomous FIB sample preparation by enabling dynamic decision-making based on real-time image inference rather than fixed process scripts. The methodology improves throughput, repeatability, and data quality while reducing dependence on operator expertise. These results demonstrate the feasibility of AI-driven autonomous endpoint detection and establish a foundation for scalable, high-throughput semiconductor failure analysis and future unmanned laboratory environments.

This paper investigates process options to fabricate reliable 420°C full Si CMOS high voltage transistors (reaching BTI 10yrs limit for both P/NMOS). The analysis of TiN based and Si-POLY gate with UV nanosecond laser annealing (UV-NLA), proves that TiN on SiO2 even at 420°C is not reliable due the O-scavenging (detrimental for NBTI). Si-POLY gate using UV-NLA activation with 420°C high pressure passivation (HPD2) reaches the 10yrs limit at VOV = 2.3V (VG = 2.5V) for both P/NMOS without hydrogen radical annealing (H∗), benefiting of UV-NLA fast high temperature transients. The interface traps creation during NBTI relies on gate materials concerning PMOS and, on passivation scheme for NMOS during PBTI stress. The analysis of CET maps suggests a significant reduction of H-E’ in SiO2, both for electron (-/0) and holes (0/+) traps using high pressure passivation.