Invited Talks
Invited Talk – Enabling Large Scale Implementation of Reliable WBG Devices from a Manufacturer’s Viewpoint
Dr. Stefano Aresu – Infineon Technologies, Austria
Wide bandgap (WBG) power semiconductors give significant advantages, but they also introduce new reliability risks and qualification demands. This talk highlights the challenges specifically shared by SiC Vertical MOSFETs and GaN Lateral HEMTs. Understanding the reliability limits of both technologies is important to meet the low-DPPM levels expected by customers and already achieved by mature Silicon MOSFETs. Dedicated dynamic measurements are needed to reveal new degradation mechanisms and develop related failure models. In addition, there is the desire to provide universal degradation models for each technology to be applied to a large portfolio of products with a variety of designs and application relevant needs. These insights shape our qualification strategy as a company and the demand for tailored industry-wide WBG standards. Managing extreme thermal and electrical stress during dynamic testing is particularly challenging, but it is important to balance manufacturing constraints with strict reliability targets.
The SiC Vertical MOSFET shows its advantages in high-voltage and high-power applications, leveraging high thermal conductivity and moderate-to-high switching frequencies. We review its primary degradation mechanisms and discuss reliability tests used to evaluate its robustness under realistic operating conditions. Particular attention is given to gate oxide degradation, interface state generation, threshold voltage instability, and degradation induced by repetitive switching stress. While high temperature blocking condition and gate stress are primarily used to assess static reliability and gate oxide robustness, gate switching stress and other dynamic tests are essential for investigating mechanisms that arise under application-relevant switching conditions, as well as for defining production screening limits and guard bands to ensure the highest quality.
Similar to the SiC MOSFET, the GaN Lateral HEMT requires also dynamic testing to capture degradation occurring only under switching stress. GaN devices show their advantages for medium-voltage and medium-power applications with their ultra-low specific on-resistance and ultra-high switching frequencies. Operating under extreme conditions introduces degradation mechanisms that a traditional qualification strategy may not reveal. Characterizing these mechanisms can ensure high reliability for large-scale deployment.
Dr. Stefano Aresu received his degree in electronic engineering from the University of Cagliari in 2000. He then joined IMEC, where he focused on hot carrier effects in power devices. After earning his Ph.D. in physics in 2005, he joined the Central Reliability Department at Infineon Technologies as a Reliability Engineer responsible for qualifying automotive and industrial power devices. His research included investigations on NBTI and hot carrier effects as well as the development of device life time models. Over the past few years, he has been responsible for process qualifications and transfers for advanced smart power technologies. As a Lead Principal Engineer, he currently serves as the overall coordinator for front-end reliability topics, implementing methods ranging from single devices to full products, including eFlash and RRAM memories. He is the author and co-author of over 30 papers and patents in microelectronics reliability and actively contributes to JEDEC and AEC-Q100 standards.
Invited Talk – Ultra-Reliable All-Liquid Interconnections for Power Electronics Components
Francesco Iannuzzo – Polytechnic of Turin, Italy
Power semiconductors are vulnerable to thermo-mechanical stress due to the use of solid-metal interconnect technologies such as wire bonding, soldering, and sintering. This presentation showcases a successful usage of room-temperature Gallium-based liquid-metal pastes for chip-level packaging of SiC MOSFETs. All chip-critical interconnects (die-attach, topside, and gate connections) are implemented using liquid-metal, which remains liquid during operation. We tested the SiC MOSFETs for thermal and reliability performance. Liquid-metal packaged SiC MOSFETs showed improved thermal performance and an order of magnitude increase in power cycling lifetime. Notably, the liquid-metal pastes are contained without the use of any encapsulation.
Francesco Iannuzzo is a professor of reliable power electronics with the Power Electronics Innovation Center (PEIC) at Politecnico di Torino, Italy. His research focuses on the reliability of wide-bandgap power devices (SiC MOSFETs, GaN HEMTs), their modeling and characterization, condition monitoring, simulation, and new driving concepts to improve reliability.
Prof. Iannuzzo is the author or co-author of over 350 publications in journals and international conferences, five book chapters, and an edited book on Modern Power Electronic Devices. He has delivered over 50 technical seminars, keynotes, and several invited speeches on power electronic device reliability at top-tier conferences, including ISPSD, IRPS, EPE, ECCE, PCIM, and APEC.
Furthermore, he is a Fellow of the U.S. Institute of Electrical and Electronics Engineers (IEEE). He has served as General Chair of ESREF 2018, IWIPP 2022 (International Workshop on Integrated Power Packaging), and EPE-ECCE Europe 2023.
Invited Talk – From Device Reliability to System Reliability: Challenges Across the Photonics Value Chain
Michael Rogers – Senior Director Quality, ams OSRAM AG
Digital photonic products are increasingly complex systems comprising semiconductor devices, optical post-processing layers, advanced packaging technologies, interconnect structures, and optoelectronic assemblies.
While significant progress has been made in understanding the reliability of individual photonic components—including LEDs, VCSELs, photodiodes, and SPADs—industrial experience shows that many field reliability issues originate from downstream processing, component integration, and system-level interactions. This presentation examines reliability from a broader product perspective, addressing the complete photonics value chain, from device fabrication to long-term performance in end applications. Particular emphasis is placed on reliability risks introduced during downstream processing and system integration. Examples include silicon post-processing technologies such as through-silicon vias (TSVs), color and interference filters, handling- and assembly-induced defects, interconnect degradation, corrosion phenomena, contamination effects, and package-induced thermomechanical stresses. These mechanisms can create latent defects or accelerate degradation processes that become apparent only during prolonged environmental exposure or field operation.
Through selected industrial examples, the presentation illustrates how reliability risks evolve and propagate across increasingly integrated photonic products. Particular attention is given to the interfaces between semiconductor devices, optical post-processing layers, interconnect technologies, packaging elements, and other structural components of the system architecture. The discussion demonstrates how interactions among these elements can create complex failure paths that may not be evident when components are assessed in isolation. In some cases, system-level reliability requirements and integration-related failure mechanisms ultimately necessitate changes to the design of individual components, highlighting the strong interdependence between device design and product architecture.
Building on these observations, the presentation highlights the importance of understanding the physical architecture of photonic systems. Reliability risks frequently originate at interfaces where optical, electrical, thermal, mechanical, and environmental sensitivities interact, creating cross-dependencies that may remain hidden when components are evaluated independently. A thorough understanding of component sensitivities, interface behavior, and resulting cross-dependencies is therefore essential for identifying and mitigating system-level failure mechanisms. Risk-management methodologies such as DFMEA are valuable tools, but their effectiveness ultimately depends on a sound understanding of the underlying architecture and interaction mechanisms. This broader perspective supports a shift from a purely component-centric view of reliability toward a system-level understanding of photonic products. By linking physical degradation mechanisms to architectural interfaces and component interactions, reliability can be assessed in terms of customer-relevant outcomes such as sensitivity loss, accuracy degradation, parametric drift, reduced signal-to-noise ratio, or catastrophic failure. This perspective provides a more effective framework for identifying and mitigating reliability risks in increasingly integrated photonic systems.
While component reliability remains the foundation of robust photonic products, increasingly integrated systems demand a broader reliability perspective. Understanding system architecture, component interfaces, and integration-related interactions is essential for managing reliability risks and preserving functional performance throughout product lifetime. Meeting future challenges will require a holistic reliability approach spanning the entire photonics value chain—from device physics to system architecture.
Dr. Michael Rogers is Senior Director of Quality and Head of Technology Quality Engineering at ams OSRAM, where he is responsible for quality engineering in new technology development and leads the global reliability and failure analysis laboratories for the Light Sensing and Photonics business. He received a Diplomingenieur degree (equivalent to an MSc) in Technical Chemistry, a Doctorate in Technical Physics, and a Master of Advanced Studies in Nanotechnology and Nanoanalytics from Graz University of Technology. He began his career in electron microscopy and semiconductor failure analysis, specializing in focused ion beam (FIB), transmission electron microscopy (TEM), and advanced materials characterization. Since joining ams OSRAM in 2007, he has held roles spanning defect engineering, process integration, product reliability, and global quality and reliability leadership. His professional interests include semiconductor reliability, optical sensing technologies, failure analysis, and reliability engineering across the photonics value chain.
Invited Talk – Cryogenic low-noise amplifiers for quantum computing: Engineering noise and thermal properties
Cezar Zota – IBM Research Europe, Switzerland
Cryogenic low-noise amplifiers are essential parts of today’s quantum computers and are primarily employed in the readout path at the 4 K stage to read the qubit states. Their performance and reliability directly impact the quantum computations, e.g. through the readout fidelity. As one of the few active, i.e. power-dissipating, cryogenic devices used already today, there are strict requirements placed in terms of noise-levels, power, stability and robustness. To support ever increasing qubit numbers, improved amplifiers will be desirable in the future. In this presentation, we demonstrate our cryogenic III-V high-electron mobility transistor technology based on the InGaAs/InP system. We show how noise properties depend on temperature, and how this dependence arises from various traps and defects across the heterostructure that can be effectively suppressed with quantum well engineering. We also describe thermal effects, in particular self-heating, which is one of the primary limits of noise and reliability in these devices. Several self-heating measurement methodologies are examined, such as quantum thermometry, which is able to determine both the intrinsic electron temperature as well as associated scattering mechanisms throughout the device self-heating process. Power semiconductors are vulnerable to thermo-mechanical stress due to the use of solid-metal interconnect technologies such as wire bonding, soldering, and sintering. This presentation showcases a successful usage of room-temperature Gallium-based liquid-metal pastes for chip-level packaging of SiC MOSFETs. All chip-critical interconnects (die-attach, topside, and gate connections) are implemented using liquid-metal, which remains liquid during operation. We tested the SiC MOSFETs for thermal and reliability performance. Liquid-metal packaged SiC MOSFETs showed improved thermal performance and an order of magnitude increase in power cycling lifetime. Notably, the liquid-metal pastes are contained without the use of any encapsulation.
Dr. Zota received the PhD degree in Electrical Engineering from Lund University, Sweden, in 2017. Since then, he has been a Staff Research Scientist and Master Inventor at IBM Research Europe – Zurich. His research interests include cryogenic electronics for quantum computing, including III-V amplifiers, cryo-CMOS, and cryogenic modelling. More recently, his work has also focused on state-of-the-art CMOS technologies, in particular for the back-end-of-line. He is the recipient of an Ambizione career grant from the Swiss National Science Foundation, is a member of the National Centre of Competence in Research SPIN, has coordinated several European research projects, and holds over 20 patents and has co-authored over 80 peer-reviewed publications in the field of electron devices.
